1. Technical Field
The present invention relates to high voltage devices with improved resistive field shields and, more particularly, to high voltage devices with resistive field shields comprising a layer of semi-insulating silicon nitride (sin-SiN).
2. Description of the Prior Art
The breakdown voltage and/or leakage current of high voltage discrete devices and integrated circuits will be degraded by the presence of charge (usually ionic) on the top surface of the outermost passivation layer. These mobile charges may also form a surface channel which can effectively create a shunt resistor between the emitter-base, emitter-collector, or collector-base electrodes. In the presence of an electric field, high temperature, and/or moisture, these surface ions can redistribute and create large extrinsic potentials on the surface of the chip. Additionally, cracks or pinholes in the top passivation layer will allow charge to leak up into or on top of this layer and spread out from the point of origination. If the potential generated by this leakage charge is different from that of the silicon below it, field crowding results, leading to a degradation of both the breakdown voltage and leakage current of the high voltage device.
A technique for limiting this effect is to shield the surface of the device from the effects of the charge by using a resistive field shield which contacts the surface and makes electrical contact to conductors on the surface. A semi-insulating polysilicon (SIPOS) layer may be used as such a shield. A description of this type of field shield may be found in the article entitled "Characterisation and modelling of SIPOS on silicon high-voltage devices" by J. N. Sandoe et al. appearing in IEE Proceedings, Vol. 132, Pt. 1, No. 6, December 1985 at pp. 281-3. One problem created by the use of a SIPOS shield layer is that it introduces leakage which may be greater than is acceptable in some applications (extreme high voltage applications, for example).
One technique for increasing the effectiveness of a SIPOS field shield is disclosed in U.S. Pat. No. 4,580,156 issued to R. B. Comizzoli on Apr. 1, 1986. A segmented SIPOS layer is used by Comizzoli as a resistive field shield, where the segmentation of the layer significantly increases the resistance thereof and thereby limits the leakage generated by the layer. The segmentation, however, adds to the complexity of the device fabrication process. An alternative method of improving SIPOS passivation is disclosed in U.S. Pat. No. 4,297,149 issued to P. R. Koons et al. on Oct. 27, 1981. This method requires the annealing of the device at a temperature of approximately 550.degree. C. prior to metallization and alloying of the metal electrodes at a temperature less than 425.degree. C. It is thought that this temperature control technique changes the types of oxygen-silicon bonds present in the SIPOS layer so as to improve the device performance. However, the device may never again be exposed to temperatures greater than 425.degree. C., or the breakdown problem will return.
As a material, SIPOS has further problems which limit its usefulness as a passivation material. Firstly, SIPOS is extremely reactive in a humid environment, experiencing drastic conductivity changes (both increases and decreases) which are neither well-controlled nor well-understood. In particular, when SIPOS is in contact with aluminum metallization, the aluminum will penetrate the surface, forming Al.sub.2 O.sub.3 at the interface. Thus, SIPOS is essentially limited to utilization with devices encased to hermetic packages, resulting in increasing the cost (and perhaps size) of the final packaged device. Additionally, when SIPOS is used with tri-level metal contacts (Ti-Pt-Au), the gold will migrate through the contact, forming various eutectic compounds with the SIPOS. Again, these compounds will seriously degrade the performance of the device.
Thus, a need remains in the prior art for a resistive field shield for high voltage devices which overcomes these and other limitations associated with SIPOS resistive field shields.